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ECSE Departmental Research Seminar, 01-03-2006

Title: "Asynchronous Self Timed Processing"

Speaker: Damien Browne, E&CSE, Monash University

Abstract:

Nearly all commercially available processing systems have a clock and digital sequential designed; we refer to these circuits as synchronous in this report. The period of this clock is based on the worst case delay through its various combinational logic blocks. The clock is typically globally distributed. Asynchronous circuits can, with the application of a number of techniques, overcome these two disadvantages.

Currently, however, the problem of performance relies on the designer to intuitively spot features in algorithms that can be exploited to give a fast average case performance. The most well documented case is that of a self timed adder. This research proposes to remove the guesswork normally associated with these circuits and algorithms and to find definitive techniques for circuit creation so that self timed designs can compete with synchronous designs in size, speed and power usage. In addition the research aims to find under what circumstances and which algorithms are more suited to be implemented in a self timed system.

About the speaker:

Damien completed his Bachelor of Computer Systems Engineering at Monash University in 2004. Damien's supervisor is A/Professor Lindsay Kleeman. His research interests are digital processing and reconfigurable hardware.
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Visitors Information
A map of the Clayton Campus of Monash University indicates the venue, Building 72, and visitor parking on the top floor of the North carpark, Building 76.

Limited reserved parking spaces are available for visitors attending the seminar. (Requests for parking should be made in advance)